This invention relates to a large-capacity memory with buffers, and specifically to a memory device having buffers such as serial memories, and shift registers.
A switching hub is known as one of network equipment or apparatuses used when information held in the same segment is transferred from a given personal computer to another personal computer under a network environment. A shared memory for constructing the switching hub is known as a conventional general-purpose DRAM, SRAM or an SDRAM (Synchronous DRAM) that will be widely used for a general-purpose DRAM from now on. Further, the switching hub needs a buffer unit, which makes use of a general-purpose SRAM or a small-capacity FIFO (First-In, First-Out) type SRAM.
Most of switching hubs are comprised of a general-purpose X-16 DRAM or SRAM or an X-16 SDRAM, i.e., they are constructed using discrete devices. Examples developed with SDRAMs capable of sync-clock control have been on the increase in recent years.
With a view toward implementing a device whose processing speed is faster (i.e., whose number of processing bits per unit time is large), an I/O needs to extend its width broader. Since, the I/O width is represented as an X16 even at the maximum in a world-standardized general-purpose memory, a large number of X16-configured memories are only used in parallel to design a device having a broader width such as an X32 or X64 or the like. In other words, the implementation of the device will result in an unavoidable increase in cost.
Further, the FIFO (or SRAM) used as a buffer connected to the memory referred to above also makes a common use of the X16-configured product in the same manner as described above. As described above, the implementation of the device larger in I/O width needs a large number of devices. When it is desired to increase the number of ports, a larger number of FIFOs are required. As a result, the device itself will be very expensive.
Moreover, a drawback arises in that since electrical wiring for connecting to shared memory portions broadened in I/O width are implemented or provided in plural form, (a great number of data buses are needed) and hence buffers wide in I/O width need broader board areas on a board. This can result in a delay in the speed for the transfer of data between the FIFO and the shared memory.
Thus, the design of the device using the conventional discrete devices makes it impossible to construct a high-performance and economical system having an I/O width represented as an X128 or X256, for example.